1. Field of the Invention
The present invention generally relates to testing of integrated circuits, and more particularly, to the debugging of complex application specific integrated circuits (ASICs).
2. Description of the Related Art
Many modem electronic devices are now implemented using application specific integrated circuits (ASICs). ASICs are computer chips designed for a specific application, and are typically built by connecting existing circuit building blocks. Since the building blocks may already exist in a library, it is much easier to produce a new ASIC than to design a new chip from scratch. As the feature size of integrated circuits has grown smaller, the level of integration (i.e., the number of gates) available in ASICs has grown. With this increase has come increased complexity in all stages of the integrated circuit (IC) design process, particularly the testing phase.
Testing ASICs means more than just designing for test. Although today""s sophisticated design-for-test (DFT) tools are a big step forward from earlier ones, testing is still a difficult process. One area of particular concern is trying to make sure that the devices will be testable when the silicon finally arrives. For complex designs this requires much more than just the utilization of an automatic-test pattern-generation (ATPG) package. Even with these automated tools, test-development can still take months and, in the case of mixed-signal ICs, sometimes stretches to over a year.
Very complicated ASICs (e.g., those with over a million gates), are particularly difficult to debug. This problem is exacerbated when the test is performed when the ASIC is in a system. The potential errors can be hard to identify due to the very low visibility into the chip. One prior art solution to this problem is functional, or edge-connector test. In this test a system board is coupled to test hardware (e.g., a programmable test computer), that applies particular input to the board and then monitors the board""s output to see if the expected results are obtained. This method has a number of drawbacks. First, the test code must generally be manually written. Also, the test code may be slow, depending on how long it takes to get the board set up to the particular test state. Furthermore, the testing is based on the board function, not the underlying circuit structure. Finally, the testing is typically limited to input/output (I/O) only, since only I/O ports are visible with this method.
A second prior art solution is a so-called in-circuit test using a bed-of-nails tester. A bed-of-nails-tester uses expensive testers and fixtures that physically connect to test points on a board. While this method gives better test resolution than the edge-connector test, it too has a number of limitations. First is the high cost of having custom fixtures made. Second, some modem boards are difficult to test with these testers (e.g., double-sided boards, those with fine lead pitch devices). Finally, the tests are still limited to the device stage (i.e., there is no way to see inside a complex ASIC).
In order to address a number of these drawbacks, a third solution called boundary scan technology was developed. ICs designed to support boundary scan functionality typically include a set of control and data pins which allow test data and results to be shifted into and out of the device. The test paths within the devices allow certain registers to be preloaded with test patterns, and then the device can be clocked and the results shifted out. One organization, the Joint Test Action Group (JTAG) developed a standard for boundary scan technology in the mid 1980""s (now IEEE Std. 1149.1).
While JTAG provides a substantial improvement over other prior art test methods, it still does not satisfy all test needs, particularly for highly complex high-speed ASICs. In particular, it is difficult to monitor in real-time the inner workings of an ASIC being tested because the boundary scan methodology typically utilizes a serial shift out of test data on the ASIC""s own output pins. In addition, there are no provisions for allowing direct real time access to wide internal buses deep within the ASIC. For these reasons, a system and method for allowing real time observability into complex ASICs is needed.
The problems outlined above may at least in part be overcome by a system and method for testing integrated circuits in accordance with the present invention. In one embodiment, such a system and method utilize special logic that allows the multiplexing of different critical busses so that the signals on the critical busses may be output for observation via selected test pins on the integrated circuit. Unlike prior art boundary scan devices, the information from the selected critical bus may be output in parallel in real time. Advantageously, this may make testing and/or debugging the integrated circuit design more accurate and less time consuming.
In one embodiment, an integrated circuit utilizing the system for testing may include a plurality of functional units connected by a plurality of internal buses. The integrated circuit may include a plurality of pins (xe2x80x9cfunctional pinsxe2x80x9d), typically located on the periphery of the integrated circuit, used for interfacing with other integrated circuits or devices. In order to enable efficient and accurate testing and debugging of the functional blocks, it may be advantageous to be able to monitor signals on some or all of the internal busses connecting some or all of the functional units. To accomplish this, the integrated circuit may also include one or more control pins and/or test pins, also typically located on the periphery of the integrated circuit, used for debugging the ASIC. The integrated circuit may also include multiplexing logic comprised in the integrated circuit and connected to some or all of the internal buses and/or functional units. The multiplexing logic may be configured to select one of the internal buses or functional units in response to one or more control signals conveyed to the multiplexing logic via the control pins. The multiplexing logic may be configured to output signals from the selected internal bus or functional unit to the test pins in real-time and preferably in parallel.
In some implementations, the multiplexing logic may be configured to switch slowly relative to the internal buses and/or functional units. Advantageously, this may allow the multiplexing logic to be implemented on the integrated circuit using smaller transistors, thereby preserving precious real estate on the die.
A method for testing integrated circuits is also contemplated. In one embodiment, the method includes conveying one or more control signals to one or more test control pins on an integrated circuit that is to be tested. The control signal or signals cause the selection logic within the integrated circuit to select one of a plurality of internal buses and/or functional units for output to a set of parallel output pins on the integrated circuit. Software for automatically determining the size of multiplexing logic to allow a particular set of internal buses and/or states to be individually monitored is also contemplated. Software for performing automated testing of the integrated circuit using the methods described herein is also contemplated.